Qualcomm AI Engine Direct - support SW6100 #16003
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Summary - Support SOC SW6100 Test plan - Use unit test with -m SW6100
🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/16003
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@cccclai @haowhsu-quic |
| QcomChipset.SXR2330P: SocInfo(QcomChipset.SXR2330P, HtpInfo(HtpArch.V79, 8)), | ||
| QcomChipset.QCS9100: SocInfo(QcomChipset.QCS9100, HtpInfo(HtpArch.V73, 8)), | ||
| QcomChipset.SAR2230P: SocInfo(QcomChipset.SAR2230P, HtpInfo(HtpArch.V81, 4)), | ||
| QcomChipset.SW6100: SocInfo(QcomChipset.SW6100, HtpInfo(HtpArch.V81, 4)), |
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@billmguo mentioned in the email saying it should be v79 HTP + 2MB vtcm, can we double check?
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The data was collected in internal QNN codebase. Since we don't have the corresponding device, could you try this configuration on your side?
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The data was collected in internal QNN codebase. Since we don't have the corresponding device, could you try this configuration on your side?
Referring to QC doc 80-74841-45 Rev. AA Qualcomm® Hexagon Tensor Processor Overview for SW6100, it states v79 HTP, but doesn't mention VTCM size. Is the doc inaccurate or outdated?
| QcomChipset.SXR2330P: SocInfo(QcomChipset.SXR2330P, HtpInfo(HtpArch.V79, 8)), | ||
| QcomChipset.QCS9100: SocInfo(QcomChipset.QCS9100, HtpInfo(HtpArch.V73, 8)), | ||
| QcomChipset.SAR2230P: SocInfo(QcomChipset.SAR2230P, HtpInfo(HtpArch.V81, 4)), | ||
| QcomChipset.SW6100: SocInfo(QcomChipset.SW6100, HtpInfo(HtpArch.V81, 4)), |
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SW6100 seems should be v79, 2MB VTCM not v81 4MB VTCM
| QCS9100 = 77 # v73 | ||
| SAR2230P = 95 # v81 | ||
| SA8255 = 52 # v73 | ||
| SW6100 = 96 # v81 |
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Is there any formal doc can get the socid SW6100
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we have tried this it worked in our HW thanks approve the diff
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Can you rebase to trigger the CI? |
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Summary
Test plan